Conventionally, a telecast mode for transmitting data of telecast utilizing a vertical blanking period of a video signal has generally been known as a method for transmitting data using serial transmission. In various regions throughout the world, data of telecasts are transmitted utilizing vertical blanking periods of video signals. FIG. 15 shows the types of telecasts employed in the respective regions in the world, superimposition lines where telecasts are superimposed, and transmission clocks. In order to calculate slice levels of telecast data of these telecasts, a data slice control device as shown in FIG. 14 has conventionally been employed (refer to “Description of MN102H51K/F51K/57K/F57K LSI, Chapter 9: Caption Decoder, P295-332, [online], May, 2000, Matsushita Electric Industrial Co., Ltd. Semiconductor Company [searched on Jun. 9, 2003], the Internet <URL: https://www.semicon.panasonic.co.jp/cgi-bin/micom/manual/download/dwld_products.cgi?email=general&passwd=generaluser&mode=general&lang=3&type=0&series=MN102H00>). Hereinafter, the construction and operation of the conventional data slice control device will be described with reference to FIG. 14.
In FIG. 14, a video signal input terminal 1401 receives an analog video signal S1401 in which telecast data are superimposed in a vertical blanking period.
An A/D converter 1402 samples the analog video signal S1401 with a predetermined sampling clock fs (MHz) to convert the analog video signal S1401 into a digital video signal S1402, and outputs the digital video signal S1402 to a low-pass filter (LPF) 1403.
The LPF 1403 subjects the inputted digital video signal S1402 to noise removal, and outputs the noise-removed digital video signal S1403 to a maximum value detection circuit 1404, a minimum value detection circuit 1405, and a binarization circuit 1414.
A sync separation circuit 1419 separates the inputted digital video signal S1402 into a horizontal sync signal S1419a and a vertical sync signal S1419b, and outputs these signals to a clock run-in (CRI) period setting circuit 1418. The horizontal sync signal S1419a and the vertical sync signal S1419b are used for setting the position of a CRI period.
The CRI period setting circuit 1418 generates a CRI period setting signal S1418 for setting a CRI period of the telecast data superimposed on the digital video signal S1402, on the basis of the vertical sync signal S1419b and the horizontal sync signal S1419a, and outputs the CRI period setting signal S1418 to the maximum value detection circuit 1404 and the minimum value detection circuit 1405.
The maximum value detection circuit 1404 detects a maximum value S1404 of the amplitudes at the sampling points of the digital data within the period that is set by the CRI period setting signal, on the basis of the CRI period setting signal S1418 obtained from the CRI period setting circuit 1418 and the noise-removed digital video signal S1403, and outputs the maximum value S1404 to a slice level calculation circuit 1413.
The minimum value detection circuit 1405 detects a minimum value S1405 of the amplitudes at the sampling points of the digital data within the period that is set by the CRI period setting signal, on the basis of the CRI period setting signal S1418 obtained from the CRI period setting circuit 1418 and the noise-removed digital video signal S1403, and outputs the minimum value S1405 to the slice level calculation circuit 1413.
The slice level calculation circuit 1413 calculates a slice level S1413 using the maximum value S1404 and the minimum value S1405, and outputs the slice level S1413 to the binarization circuit 1414.
The binarization circuit 1414 converts the noise-removed digital video signal S1403 into a binarized signal S1414 comprising 0 and 1 at the slice level S1413, and outputs the binarized signal S1414 to a sampling circuit 1415.
The sampling circuit 1415 samples the binarized signal S1414 that is obtained in the binarization circuit 1414, at predetermined sampling intervals according to the type of the telecast mode, and outputs sampled data S1415 to a decoding circuit 1416.
The decoding circuit 1416 converts the serial sampled data S1415 into a parallel signal, subjects the parallel signal to a decoding process according to the telecast type, such as error correction, and outputs the decoded data S1416 through an output terminal 1417 to the outside.
In the conventional data control device shown in FIG. 14, however, the CPI period setting signal is generated on the basis of the horizontal sync signal obtained from the sync separation circuit, and a maximum value and a minimum value of the amplitudes of the data within the period indicated by the CRI period setting signal are calculated, and then the slice level of the telecast data is calculated using the maximum value and the minimum value. Therefore, the following drawbacks may occur.
That is, there are cases where the horizontal sync signal separated by the sync separation circuit may be disturbed by such as a macrovision signal of a copy guard signal that is superimposed in the vertical blanking period. Then, the CRI period setting signal is also disturbed, whereby the CRI period setting signal cannot be generated in a desired position, and an optimum slice level cannot be calculated.